Title: FPGA Design Flow for 8-bit ALU using Xilinx ISE
Authors: Dharmavaram Asha Devi
Abstract: The proposed paper describe an 8-bit Arithmetic & Logic Unit design steps in front end VLSI Design flow. This design is verified by RTL simulation, synthesized, and implemented using Xilinx ISE Software. The functionality is verified in the target FPGA, Spartan 3E. The advantages of FPGA based designs are less time to market, low NRE cost, in-system programmability and high reconfiguration. Of course, FPGA verification is a must before the back end flow of either ASIC or IC design flow. Even though 32 or 64 bit processors available in advanced computer systems, there is a demand for 8-bit ALUs for many embedded applications. The proposed ALU is designed using Verilog HDL.
Title: Design of High Performance Rc4 Stream Cipher
Authors: N P. Sarada Devi, G.Lakshmi and K. Manjula
Abstract: RC4 protocol is most popular Cipher in Cryptography. In this paper, we present the study of the efficient design of RC4 stream cipher, and proposing the efficient architecture for cipher. The concept of loop unrolling and pipeline combined to produce the 2 RC4 keystream bytes per clock cycle. The design is compared with the previous proposed paper and to check the how much cycles required for complete the individual KSA and PRGA modules and together the RC4 Stream Cipher. The Design is built using the XILINX 13.2 on Vertex ML605 Evaluation FPGA Board.
Title: A New iterative triclass thresholding technique for Image Segmentation
Authors: M.M.Raghavendra, S.Priyanka and S.Samiullah
Abstract: We present a new method in image segmentation that is based on Otsu?s method but iteratively searches for sub regions of the image for segmentation, instead of treating the full image as a whole region for processing. The iterative method starts with Otsu?s threshold and computes the mean values of the two classes as separated by the threshold. Based on the Otsu?s threshold and the two mean values, the method separates the image into three classes instead of two as the standard Otsu?s method does. The ?rst two classes are determined as the foreground and background and they will not be processed further. The third class is denoted as a to-be-determined (TBD) region that is processed at next iteration. At the succeeding iteration, Otsu?s method is applied on the TBD region to calculate a new threshold and two class means and the TBD region is again separated into three classes, namely, foreground, background, and a new TBD region, which by de?nition is smaller than the previous TBD regions. Then, the new TBD region is processed in the similar manner. The process stops when the Otsu?s thresholds calculated between two iterations is less than a preset threshold. Then, all the intermediate foreground and background regions are, respectively, combined to create the ?nal segmentation result. Tests on synthetic and real images showed that the new iterative method can achieve better performance than the standard Otsu?s method in many challenging cases, such as identifying weak objects and revealing ?ne structures of complex objects while the added computational cost is minimal.
Title: Applications of Artificial Neural Networks in Image Processing and Segmentation
Authors: A. Srinivasa Reddy and G. Malleswari
Abstract: Since last few years, a significant progress in both the hypothetical aspects and the applications of neural networks on the image analysis, and processing, has been made. Artificial Neural Networks (ANNs) are supporting tools for image processing. ANNs conserve their role as non-parametric classifiers, non-linear regression operators, or (un)supervised feature extractors. The applications of ANN methodology includes all the steps of the image processing chain, starting from data pre-processing and reduction, image segmentation, up to object recognition and scene understanding.
Title: A 65-nm CMOS Implementation of Efficient PLL Using Self - Healing Prescalar
Authors: S.Md.Imran Ali, Syed Noorullah and Shaik Naseer Ahamed
Abstract: Nanometre scale technology introduces several issues in CMOS technology such as variability and leakage current that significantly affect the circuit performance. Devices performances plunge when variability is introduced inadvertently due to process variations causing device mismatching. Leakage currents are the main cause of malfunction of circuits at nano scale; they also degrade accuracy of analog circuits and make digital circuits to malfunction. Phase Lock Loops which are widely used in different application when made at 65nm technology face several functional and performance issues due to leakage currents which alter the states of digital systems and make analog systems less accurate. Calibrated Charge Pump, self healing prescaler self healing VCO are used in Phase locked loop to overcome above issues. In 65nm technology of CMOS with an active area of 0.0182 mm2 PLL is fabricated.
Title: Intelligent Scheme for Defending Against Black-Hole Attacks by Malicious Nodes in Dynamic Source Routing Protocol
Authors: R.Bhairavi and A.Santhiya
Abstract: The important characteristics of mobile ad hoc networks (MANETs) are its dynamic network topology and mobility. Thus nodes must cooperate with each other for the establishment of communication. But in the presence of virulent nodes, this kind of network is prone to several security issues. To overcome this, we proposed bait detection and prevention scheme (BDPS) in order to detect and prevent black hole attacks caused by malicious nodes in the Dynamic Source Routing (DSR) process. This scheme comprises of three steps, (i.e.,) the initial bait step, reverse tracing step and the final path detection and routing phase (FPDR). Implementation is done using Network Simulator. Thus, BDPS improves the routing performance in terms of throughput, packet delivery ratio and end to end delay.
Title: Edge and corner avoidance by a mobile robot using infrared sensors
Authors: Dheeraj sharma
Abstract: The work in this paper is directed towards the development of a robot which can move on a flat surface like that of a table top and successfully detect and avoid edges and corners by changing its path. The detection of edge and corner has been achieved by using a pair of infrared transmitter and receiver based sensor. A very basic microcontroller 89C51 has been used to carry out the control logic execution. The code which has been written in assembly language takes care of changing the direction of the moving robot after edge or corner detection by activating the dc motors connected to the wheels in a suitable manner. The operation of the robot has also been checked for successful operation on an infrared reflective surface. The final robot design is quite cost effective as it uses basic microcontroller, low range infrared sensors and motor driver integrated circuits.
Title: Design and analysis of 8-bit, 16-bit and 32-bit Shannon Adders
Authors: Sumandeep Kaur and Sharanjeet Kaur
Abstract: In this paper we have designed 16 transistors Shannon adder using Tanner EDA tool v13 and then analyzed this adder in terms of average power and delay at two voltages 0.7V and 1V. After this 8 bit, 16 bit and 32 bit adders are designed using this Shannon adder. We have also compared the stimulated results of these three adders like average power and delay at two frequencies (i) 100Hz (ii) 500Hz. The proposed Shannon adder cell gives better performance in terms of power dissipation and propagation delay as compared to conventional full adder cells.
Title: A review on ZRP protocol in MANETs
Authors: Neha Gupta and Er Maninder Singh
Abstract: MANET is a set of wireless mobile nodes having unrestricted mobility and connectivity to others. Zone Routing Protocol is a hybrid protocol which can be used in different network environments by setting appropriate zone radius. The objective of this survey paper is to study and analyze various techniques used to maximize network lifetime, to minimize delay in ZRP protocol. This paper is a survey on comparative analysis on various enhancements implemented in ZRP.
Title: Higher Order Filter Implementation on FPGA Using Distributed Arithmetic Procedure
Authors: Syed Noorullah, S.Md.Imran Ali and Shaik Naseer Ahamed
Abstract: In day to day scenario, digital signal processing makes use of Field Programmable Gate Array technology to achieve high speed that offers intense flexibility and reliability in the design with the help of parallel structure and configurable logic. By using traditional approaches for FPGA-based FIR filters cost related to multiply and accumulate blocks increases proportionally to order of the filter. To overcome this problem FIR filters adopted distributed arithmetic technique for obtaining robust design. Resource enhancement is fully achieved by using Distributed Arithmetic design and system speed is enormously increased using pipeline structures. Design complexity related to number of memory units is reduced with divided look up tables. Look-Up-Table (LUT) are made to protect the values of MAC and calling the input data when ever needed, based on Distributed Arithmetic. The hardware resources can be saved by look up table that take place of MAC units. Structure scale is decreased and MAC blocks are saved by using 31 orders FIR low-pass filter based on Distributed Arithmetic. along with increasing the speed of the system by reducing need of memory units.
Title: D.C and A.C Analysis of Common Source Amplifier with Resistive Load Connected Using Cadence Virtuoso
Authors: P. A. Irfan Khan and Shaik Mohammed Yaseen
Abstract: In this paper we are going to discuss about the common source amplifier with resistive load connected and the implementation of the CS amplifier with resistive load connected in the cadence virtuoso tool and checking the output results of D.C analysis, A.C analysis, Transient analysis and finally designing the layout of the CS amplifier with resistive load connected using cadence virtuoso 180nm Technology.
Title: A review on issues and challenges in VANETs
Authors: Poojan Verma and Er Maninder Singh
Abstract: Vehicular ad hoc networks are self configuring networks in road safety and many commercial applications. The performance of communication depends on the routing protocol. Vehicle mobility causes communication links between vehicles to be broken. Up-to-date positions of next neighbours are important criteria to be considered for making effective beaconing schemes. This paper conducts survey on traffic classification, efficiency of routing protocols, QOS metrics required for efficient communication.
Title: Multimodal Species Fusion Based on Wavelet and Curvelet Transforms
Authors: Viji.P, Saranya.C, Soundarya. L and Vanitha.S
Abstract: The content of this paper is about Comparative analysis of multimodal medical image fusion methods. This system approach is transform based fusion process. The fusion process is done between two multimodal species. Species are nothing but different kind of medical images like Magnetic Resonance Image (MRI), Computer Tomography (CT), Positrons Emission Tomography (PET), Single Photon Emission Computed Tomography (SPECT), etc. In medical image, two types of particles are present. One particle is denser tissue particles. They are mostly present in CT image which has less distortion. Another one particle is soft tissue particles they are mostly present in MR image which has more distortion. These two different particles of same organ are fused together for the extraction of informative particles. The wavelet transform based fusion is complex for the detection of particular frequency at a particular time instant. The signal quality, edge detection and shape detection in wavelet based fusion is not good. So, the curvelet transform is used for image fusion. The curvelet transform follows the ridgelet transform. The ridgelet transform is mathematically viewed in terms of radon domain. Radon domain is a tool for the shape detection. Finally the performance result is evaluated from the PSNR and RMSE values.